SHA1 with SPI interface.
The SHA1 SPI core has been ported to Actel ProASIC.
It takes Opcode (16) data (16*32) = 528 SPI clock ticks to transfer a data block.
The SHA1 algorithm runs in less clock ticks that the transfer time.
The core has been optimised for small core size. To achieve this we use SRAM to store the data to be hashed and only use one 32 bit adder.
The core uses 2922 cells (95% of an A3P125) at present and runs at 49MHz.
SHA1 with a parallel interface is also available. Please email us for more information.